Configurable Logic Block

Generality

Each Logic Block (CLB) consists of 8 Logic Elements (LEs) as shown in Fig. 23. All the pins of the LEs are directly wired to CLB pins without a local routing architecture. Feedback connections between LEs are implemented by the global routing architecture outside the CLBs.

Fig. 23 Configurable logic block schematic

Multi-mode Logic Element

Physical Implementation

As shown in Fig. 24, each Logic Element (LE) consists of

• a fracturable 4-input Look-Up Table (LUT)

• two D-type Flip-Flops (FF)

Fig. 24 Detailed schematic of a logic element

The LE can operate in different modes to map logic function efficiently

• 4-input LUT and single FF (see details in Operating mode: LUT4 + FF).

• Dual 3-input LUTs and 2 FFs (see details in Operating mode: Dual-LUT3).

• 2-bit shift registers (see details in Operating mode: Shift-Register).

Operating mode: LUT4 + FF

The logic element can operate in the Look-Up Table (LUT) + Flip-flop (FF) mode as many classical FPGA logic elements. As depicted in Fig. 25, the fracturable LUT will operate as a single-output 4-input LUT and the upper FF is used to implemented sequential logic.

The operating mode is designed to efficiently implement 4-input functions.

Fig. 25 Resource usage of the logic element operating in LUT4 + FF mode (Grey blocks and lines are unused resources).

Operating mode: Dual-LUT3

The logic element can operate in the dual Look-Up Tables (LUTs) and Flip-flops (FFs) mode as many modern FPGA logic elements. As depicted in Fig. 26, the fracturable LUT will operate as two 3-input LUTs with shared inputs.

The operating mode is designed to efficiently implement two 3-input functions with shared input variables. A popular example is the adder function, where the carry logic can be mapped to the upper LUT3 and the sum logic can be mapped to the lower LUT3.

Fig. 26 Resource usage of the logic element operating in dual LUT3 + FFs mode (Grey blocks and lines are unused resources).

Operating mode: Shift-Register

As depicted in Fig. 27, the Flip-flops (FFs) can be connected in dedicated routing wires to implement high-performance shift registers.

The operating mode is designed to efficiently implement shift registers which are widely used in buffer logic, e.g., FIFOs.

Fig. 27 Resource usage of the logic element operating in shift register mode (Grey blocks and lines are unused resources).

Operating mode: Soft Adder

As depicted in Fig. 28, the 4-input LUT can implement an 1-bit adder logic, where carry inputs and outputs are connected through dedicated carry chain wires cin and cout across logic elements. This is more delay efficient than implementing adders through the dual LUT3 mode (see details in Operating mode: Dual-LUT3).

The operating mode is designed to efficiently implement multi-bit adders.

Fig. 28 Resource usage of the logic element operating in soft adder mode (Grey blocks and lines are unused resources).

Scan Chain

There is a built-in scan-chain in the CLB where all the sc_in and sc_out ports of LEs are connected in a chain, as illustrated in Fig. 23. When Test_en signal is active, users can readback the contents of all the D-type flip-flops of the LEs thanks to the scan-chain. When Test_en signal is disabled, D-type flip-flops of the LEs operate in regular mode to propagate datapath signal from LUT outputs.

Note

The scan-chain of CLBs are connected in a chain at the top-level. See details in Scan-chain.