Architecture

Floorplan

Fig. 5 shows an overview on the architecture of the embedded FPGA fabric. The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric. I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in I/O Resources).

Tile-based FPGA architecture

Fig. 5 Tile-based FPGA architecture

Tiles

The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built:

Table 4 FPGA tile type and functionalities

Type

Capacity

Description

CLB

144
Each CLB tile consists of
- a Configurable Logic Block (CLB)
- a X-direction Connection Block (CBx)
- a Y-direction Connection Block (CBy)
- a Switch Block (SB).
This is the majority tile across the fabric to implement logics and registers.

IO-A

36
The type-A I/O is a low-density I/O tile which is designed to mainly interface
the GPIOs of the SoC.
Each I/O-A tile consists of 1 digitial I/O cell.

IO-B

12
The type-B I/O is a high-density I/O tile which is designed to mainly interface
the wishbone interface and logic analyzer of the SoC.
Each I/O-B tile consists of 9 digitial I/O cells.

Routing Architecture

The routing architecture is based on uni-directional routing tracks, which are interconnected by routing multiplexers. Fig. 6 illustrates the detailed organization of the routing architecture.

Detailed routing architecture

Fig. 6 Detailed routing architecture

The routing architecture consists the following type of routing tracks:

  • Length-1 wires (L1 wires), which hop over 1 logic block (including I/O block)

  • Length-2 wires (L2 wires), which hop over 2 logic block (including I/O block)

  • Length-4 wires (L4 wires), which hop over 4 logic block (including I/O block)

Each tile includes two routing channels, i.e., the X-direction routing channel and the Y-direction routing channel, providing horizental and vertical connections to adjacent tiles. Each routing channel consists of 40 routing tracks. See details in Table 5.

Table 5 Routing track distribution of SOFA HD FPGA

Track type

Number of tracks per channel

Length-1

4 (10%)

Length-2

4 (10%)

Length-4

32 (80%)

Total

40

Scan-chain

There is a built-in scan-chain in the FPGA which connects the the sc_in and sc_out ports of CLBs in a chain (see details in Scan Chain), as illustrated in Fig. 7.

When Test_en signal is active, users can

  • overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the SC_HEAD port

  • readback the contents of all the D-type flip-flops in the FPGA through the SC_TAIL port.

Built-in scan-chain across FPGA

Fig. 7 Built-in scan-chain across FPGA