Timing Annotation

Configurable Logic Block

The path delays in Fig. 19 are listed in Table 7.

Fig. 19 Schematic of a logic element used in SOFA HD FPGA

Table 7 Path delays of logic element in the SOFA HD FPGA

Path / Delay	TT (unit: ns)
in0 -> LUT3_out[0]	0.85
in1 -> LUT3_out[0]	0.57
in2 -> LUT3_out[0]	0.30
in0 -> LUT3_out[1]	0.86
in1 -> LUT3_out[1]	0.59
in2 -> LUT3_out[1]	0.31
in0 -> LUT4_out	1.14
in1 -> LUT4_out	0.86
in2 -> LUT4_out	0.58
in3 -> LUT4_out	0.51
LUT3_out[0] -> A	0.56
LUT4_out[0] -> A	0.58
A -> out[0]	0.88
A -> FF[0]	0.56
FF[0] -> out[0]	0.88
LUT3_out[1] -> out[1]	0.89
LUT3_out[1] -> FF[1]	0.56
FF[1] -> out[1]	0.89
regin -> FF[0]	0.58
FF[0] -> FF[1]	0.56

I/O Block

The path delays in Fig. 16 are listed in Table 8.

Table 8 Path delays of I/O circuit in the SOFA HD FPGA

Path / Delay	TT (unit: ns)
SOC_IN -> FPGA_IN	0.11
FPGA_OUT -> SOC_OUT	0.11

Routing Architecture

The path delays in Fig. 6 are listed in Table 9.

Table 9 Path delays of routing blocks in the SOFA HD FPGA

Path / Delay	TT (unit: ns)
A -> B	1.61
A -> C	1.61
A -> D	1.61
B -> E	1.38