I/O Resources

Pin Assignment

The High-Density (HD) FPGA IP has 144 data I/O pins as shown in Fig. 8.

Among the 144 I/Os,

• 29 external I/Os are accessible through the Caravel SoC’s General-Purpose I/Os (GPIOs).

• 115 internal I/Os are accessible through the Caravel SOC’s logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See Debug Mode and Accelerator Mode for details.

Warning

For all the unused GPIOs, please set them to input mode, so that the FPGA will not output any noise signals to damage other SoC components.

Note

The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes.

Warning

The internal I/O pins will drive either Wishbone or the logic analyzer, following the same truth table as mode-switch bit in Fig. 8.

Fig. 8 I/O arrangement of High-Density (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface

External I/Os

A SOFA HD FPGA IP contains 37 external I/O pins, including 29 data I/Os and 8 control I/Os.

Full details are summarized in the following table.

Table 6 SOFA HD FPGA I/O usage and sizes

I/O Type	Description	No. of Pins
Data I/O	Datapath I/Os of FPGA fabric	29
CLK	Operating clock of FPGA core	1
PROG_CLK	Clock used by configuration protocol to program FPGA fabric	1
CCFF_HEAD	Input of configuation protocol to load bitstream	1
CCFF_TAIL	Output of configuration protocol to read back bitstream	1
TEST_EN	Activate the test mode of FPGA fabric	1
SC_HEAD	Input of built-in scan-chain to load data to flip-flops of FPGA fabric	1
SC_TAIL	Output of built-in scan-chain to read back flip-flops from FPGA fabric	1
IO_ISLO_N	Active-low signal to enable I/O datapath isolation from external ports	1
Total		37

Accelerator Mode

When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor. Fig. 9 illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.

Note

Not all the 115 internal I/Os are used by the Wishbone interface. Especially, the I/O[21:29] are not connected.

Warning

The FPGA does not contain a Wishbone slave IP. Users have to implement a soft Wishbone slave when use the FPGA as an accelerator.

Fig. 9 I/O arrangement of High-Density (HD) FPGA IP when interfacing wishbone bus

Debug Mode

When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor. Fig. 10 illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations.

Note

The logic analyzer is 128-bit, while 115 bits can drive or be driven by the FPGA I/O. The other 14 bits are connected to internal spots of the FPGA fabric, monitoring critical signal activities of the FPGA in debugging purpose.

Warning

If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows:

• all the I/O directionality is set to input mode.

• all the output ports is pulled down to logic ``0``.

Fig. 10 I/O arrangement of High-Density (HD) FPGA IP when interfacing logic analyzer