Timing Annotation¶
Configurable Logic Block¶
The path delays in Fig. 19 are listed in Table 7.
Path / Delay |
TT (unit: ns) |
---|---|
in0 -> LUT3_out[0] |
0.85 |
in1 -> LUT3_out[0] |
0.57 |
in2 -> LUT3_out[0] |
0.30 |
in0 -> LUT3_out[1] |
0.86 |
in1 -> LUT3_out[1] |
0.59 |
in2 -> LUT3_out[1] |
0.31 |
in0 -> LUT4_out |
1.14 |
in1 -> LUT4_out |
0.86 |
in2 -> LUT4_out |
0.58 |
in3 -> LUT4_out |
0.51 |
LUT3_out[0] -> A |
0.56 |
LUT4_out[0] -> A |
0.58 |
A -> out[0] |
0.88 |
A -> FF[0] |
0.56 |
FF[0] -> out[0] |
0.88 |
LUT3_out[1] -> out[1] |
0.89 |
LUT3_out[1] -> FF[1] |
0.56 |
FF[1] -> out[1] |
0.89 |
regin -> FF[0] |
0.58 |
FF[0] -> FF[1] |
0.56 |