Timing Annotation
Configurable Logic Block
The path delays in Fig. 32 are listed in Table 15.
Path / Delay |
TT (unit: ns) |
---|---|
in0 -> LUT3_out[0] |
0.86 |
in1 -> LUT3_out[0] |
0.58 |
in2 -> B |
0.16 |
B -> LUT3_out[0] |
0.32 |
in0 -> LUT3_out[1] |
0.91 |
in1 -> LUT3_out[1] |
0.63 |
B -> LUT3_out[1] |
0.34 |
in0 -> LUT4_out |
1.20 |
in1 -> LUT4_out |
0.92 |
in2 -> LUT4_out |
0.78 |
in3 -> LUT4_out |
0.52 |
LUT3_out[0] -> A |
0.17 |
LUT4_out[0] -> A |
0.18 |
A -> out[0] |
0.48 |
A -> FF[0] |
0.15 |
FF[0] -> out[0] |
0.48 |
LUT3_out[1] -> out[1] |
0.47 |
LUT3_out[1] -> FF[1] |
0.16 |
FF[1] -> out[1] |
0.37 |
regin -> FF[0] |
0.15 |
FF[0] -> FF[1] |
0.16 |
I/O Block
The path delays of I/O blocks in SOFA CHD FPGA is same as the SOFA HD FPGA. See details in I/O Block.
Routing Architecture
The path delays in Fig. 6 are listed in Table 16.
Path / Delay |
TT (unit: ns) |
---|---|
A -> B |
0.81 |
A -> C |
0.81 |
A -> D |
0.81 |
B -> E |
0.57 |